6 lines
28 KiB
JavaScript
6 lines
28 KiB
JavaScript
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const lang = Object.freeze(JSON.parse("{\"displayName\":\"SystemVerilog\",\"fileTypes\":[\"v\",\"vh\",\"sv\",\"svh\"],\"name\":\"system-verilog\",\"patterns\":[{\"include\":\"#comments\"},{\"include\":\"#strings\"},{\"include\":\"#typedef-enum-struct-union\"},{\"include\":\"#typedef\"},{\"include\":\"#functions\"},{\"include\":\"#keywords\"},{\"include\":\"#tables\"},{\"include\":\"#function-task\"},{\"include\":\"#module-declaration\"},{\"include\":\"#class-declaration\"},{\"include\":\"#enum-struct-union\"},{\"include\":\"#sequence\"},{\"include\":\"#all-types\"},{\"include\":\"#module-parameters\"},{\"include\":\"#module-no-parameters\"},{\"include\":\"#port-net-parameter\"},{\"include\":\"#system-tf\"},{\"include\":\"#assertion\"},{\"include\":\"#bind-directive\"},{\"include\":\"#cast-operator\"},{\"include\":\"#storage-scope\"},{\"include\":\"#attributes\"},{\"include\":\"#imports\"},{\"include\":\"#operators\"},{\"include\":\"#constants\"},{\"include\":\"#identifiers\"},{\"include\":\"#selects\"}],\"repository\":{\"all-types\":{\"patterns\":[{\"include\":\"#built-ins\"},{\"include\":\"#modifiers\"}]},\"assertion\":{\"captures\":{\"1\":{\"name\":\"entity.name.goto-label.php\"},\"2\":{\"name\":\"keyword.operator.systemverilog\"},\"3\":{\"name\":\"keyword.sva.systemverilog\"}},\"match\":\"\\\\b([a-zA-Z_][a-zA-Z0-9_$]*)[ \\\\t\\\\r\\\\n]*(:)[ \\\\t\\\\r\\\\n]*(assert|assume|cover|restrict)\\\\b\"},\"attributes\":{\"begin\":\"(?<!@[ \\\\t\\\\r\\\\n]?)\\\\(\\\\*\",\"beginCaptures\":{\"0\":{\"name\":\"punctuation.attribute.rounds.begin\"}},\"end\":\"\\\\*\\\\)\",\"endCaptures\":{\"0\":{\"name\":\"punctuation.attribute.rounds.end\"}},\"name\":\"meta.attribute.systemverilog\",\"patterns\":[{\"captures\":{\"1\":{\"name\":\"keyword.control.systemverilog\"},\"2\":{\"name\":\"keyword.operator.assignment.systemverilog\"}},\"match\":\"([a-zA-Z_][a-zA-Z0-9_$]*)(?:[ \\\\t\\\\r\\\\n]*(=)[ \\\\t\\\\r\\\\n]*)?\"},{\"include\":\"#constants\"},{\"include\":\"#strings\"}]},\"base-grammar\":{\"patterns\":[{\"include\":\"#all-types\"},{\"include\":\"#comments\"},{\"include\":\"#operators\"},{\"include\":\"#constants\"},{\"include\":\"#strings\"},{\"captures\":{\"1\":{\"name\":\"storage.type.interface.systemverilog\"}},\"match\":\"[ \\\\t\\\\r\\\\n]*\\\\b([a-zA-Z_][a-zA-Z0-9_$]*)[ \\\\t\\\\r\\\\n]+[a-zA-Z_][a-zA-Z0-9_,= \\\\t\\\\n]*\"},{\"include\":\"#storage-scope\"}]},\"bind-directive\":{\"captures\":{\"1\":{\"name\":\"keyword.control.systemverilog\"},\"2\":{\"name\":\"entity.name.type.module.systemverilog\"}},\"match\":\"[ \\\\t\\\\r\\\\n]*\\\\b(bind)[ \\\\t\\\\r\\\\n]+([a-zA-Z_][a-zA-Z0-9_$\\\\.]*)\\\\b\",\"name\":\"meta.definition.systemverilog\"},\"built-ins\":{\"patterns\":[{\"match\":\"[ \\\\t\\\\r\\\\n]*\\\\b(bit|logic|reg)\\\\b\",\"name\":\"storage.type.vector.systemverilog\"},{\"match\":\"[ \\\\t\\\\r\\\\n]*\\\\b(byte|shortint|int|longint|integer|time|genvar)\\\\b\",\"name\":\"storage.type.atom.systemverilog\"},{\"match\":\"[ \\\\t\\\\r\\\\n]*\\\\b(shortreal|real|realtime)\\\\b\",\"name\":\"storage.type.notint.systemverilog\"},{\"match\":\"[ \\\\t\\\\r\\\\n]*\\\\b(supply[01]|tri|triand|trior|trireg|tri[01]|uwire|wire|wand|wor)\\\\b\",\"name\":\"storage.type.net.systemverilog\"},{\"match\":\"[ \\\\t\\\\r\\\\n]*\\\\b(genvar|var|void|signed|unsigned|string|const|process)\\\\b\",\"name\":\"storage.type.built-in.systemverilog\"},{\"match\":\"[ \\\\t\\\\r\\\\n]*\\\\b(uvm_(?:root|transaction|component|monitor|driver|test|env|object|agent|sequence_base|sequence_item|sequence_state|sequencer|sequencer_base|sequence|component_registry|analysis_imp|analysis_port|analysis_export|config_db|active_passive_enum|phase|verbosity|tlm_analysis_fifo|tlm_fifo|report_server|objection|recorder|domain|reg_field|reg_block|reg|bitstream_t|radix_enum|printer|packer|comparer|scope_stack))\\\\b\",\"name\":\"storage.type.uvm.systemverilog\"}]},\"cast-operator\":{\"captures\":{\"1\":{\"patterns\":[{\"include\":\"#built-ins\"},{\"include\":\"#constants\"},{\"match\":\"[a-zA-Z_][a-zA-Z0-9_$]*\",\"name\":\"storage.type.user-defined.systemverilog\"}]},\"2\":{\"na
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export default [
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lang
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]
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